1. Field of the Invention
This invention relates to integrated circuit manufacturing, and more particularly, to directing a fluid toward the surface of a CMP polishing pad at a relatively high pressure to condition the polishing pad.
2. Description of the Related Art
Fabrication of a multi-level integrated circuit involves numerous processing steps. After impurity regions have been deposited within a semiconductor substrate and gate areas defined upon the substrate, interconnect routing is placed on the semiconductor topography and connected to contact areas thereon. An interlevel dielectric is then formed upon and between the interconnect routing, and more contact areas are formed through the dielectric to the interconnect routing. A second level of interconnect routing may then be placed upon the interlevel dielectric and coupled to the first level of interconnect routing via the contact areas arranged within the dielectric. Additional levels of interconnect routing and interlevel dielectric may be formed if desired.
Unfortunately, unwanted surface irregularities may form in the topological surface of one or more layers employed by an integrated circuit. For example, a recess may result during the formation of conductive plugs which extend through an interlevel dielectric. Plug formation involves forming an opening through an interlevel dielectric and depositing a conductive material into that opening and across the interlevel dielectric. A recess may form in the upper surface of the conductive material since deposition occurs at the same rate upon the bottom of the opening as upon the sides of the opening. The formation of such recesses can lead to various problems during integrated circuit fabrication. For instance, when layers of material are formed across surfaces having recesses, step coverage problems may result. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film on horizontal regions. In general, the height of the step, e.g., the depth of the recess, and the aspect ratio of the features being covered, e.g., the depth to width ratio of the recess, affect the step coverage. The greater the step height or the aspect ratio, the more difficult it is to achieve coverage of the step without a corresponding thinning of the film that overlies the step.
The concept of utilizing chemical and mechanical abrasion to planarize and remove surface irregularities of a topological surface is well known in industry as chemical-mechanical polishing ("CMP"). A typical CMP process involves placing a substrate, e.g., a semiconductor wafer face-down on a polishing pad which is fixedly attached to a rotatable table or platen. Elevationally extending portions of the downward-directed wafer surface are positioned such that they contact the rotating pad. A fluid-based chemical, often referred to as a "slurry" is deposited upon the pad possibly through a nozzle such that the slurry becomes disposed at the interface between the pad and the wafer surface. The slurry initiates the polishing process by chemically reacting with the surface material being polished. The polishing process is facilitated by the rotational movement of the pad relative to the wafer (or vice versa) to remove material catalyzed by the slurry. Thus, while the surface of the wafer is being polished, excess material is being removed from the wafer.
The polishing pad may be made of various substances. Typically, it is desirable to use a polishing pad which is both resilient and, to a lesser extent, conformal. The selection of pad weight, density, and hardness often depends on the material being polished. A popular polishing pad comprises polyurethane which, in most instances, does not include an overlying fabric material. An example of a somewhat hard polishing pad is the IC-1000 type pad commercially available from Rodel Products Corporation. A relatively soft pad is the SUBA 500 type pad, also manufactured by Rodel Products Corporation. Unfortunately, polishing pads used for wafer planarization may undergo a reduction in polishing rate and uniformity due to loss of sufficient surface roughness. Furthermore, the pores of polishing pads may become embedded with depleted slurry particles or polishing by-product. If the pores remain blocked over a substantial period of time, a condition known as "glazing" occurs. Glazing results when enough particles build-up on the polishing pad surface that the wafer surface begins to hydroplane over the surface of the pad. Hydroplaning eventually leads to substantially lower removal rates in the glazed areas.
A method known as pad conditioning is generally used to counter smoothing or glazing of the polishing pad surface and to achieve a relatively high and stable polishing rate. Pad conditioning is herein defined as a technique used to maintain the polishing pad surface in a state which enables proper polishing of a topological surface. Pad conditioning is typically performed by mechanically abraiding the pad surface in order to renew that surface. Such mechanical abrasion of the pad surface may roughen the surface and remove particles which are embedded in the pores of the polishing pad. Opening the pores permits the entrance of slurry into the pores during CMP to enhance polishing. Additionally, the open pores provide more surface area for polishing.
An example in which a polishing pad is conditioned concurrent with wafer polishing is shown in FIG. 1. FIG. 1 provides a perspective view of a polishing pad 10 mounted on a rotatable platen 12. Platen 12 rotates about a central axis 14 along the direction shown by arrow 16. Platen 12, including pad 10, can be directed upward against wafer 18 (or vice versa). Wafer 18 is secured in a rotatable position about axis 20 by an arm 22. Wafer 18 is mounted such that the frontside surface extends against pad 10, the frontside surface embodying numerous topological features used in producing an integrated circuit. Wafer 18 rotates about axis 20 along arrow 24 within a plane parallel to the plane formed by the polishing surface of pad 10.
Wafer 18 occupies a portion of the polishing surface, denoted as a circular track 26 defined by the rotational movement of pad 10. Track 26 is conditioned during wafer polish by a conditioning head 28. Conditioning head 28 is mounted on a movable arm 30 which can swing in position along track 26 commensurate with arm 22. Arm 30 presses an abrasive surface of conditioning head 28 against the polishing surface of pad 10 predominantly within track 26 as pad 10 rotates about axis 14. During this process, protrusions on the abrasive, downward-facing surface of head 28 extend toward the surface of polishing pad 10. Particles embedded in the pores of pad 10 are thus removed from the pad and flushed with slurry across the pad surface. As the slurry is introduced, the removed particles are rinsed over the edges of the polishing pad into a drain (not shown). Removing the particles from the polishing pad enables the depleted pad surface to be recharged with new slurry. The abrasive surface of conditioning head 28 may also function to roughen the surface of pad 10. FIG. 1 illustrates conditioning concurrent with wafer polishing; however, it is recognized that conventional conditioning can occur either before or after wafer polishing.
FIG. 2 depicts a cross-sectional view of the CMP and conditioning process illustrated in FIG. 1. More specifically, FIG. 2 illustrates the abrasive surface 32 formed at the lower surface of conditioning head 28. Abrasive surface 32 extends as a plurality of protrusions interspersed with recesses. The protrusions and recesses can be spaced close together or farther apart depending on the porosity of pad 10. Surface 32 preferably contacts the surface of pad 10 commensurate with wafer 18. More particularly, abrasive surface 32 extends below the upper surface of slurry film 34 to dislodge depleted slurry particles and/or wafer polish by-product from pores of pad 10. A problem associated with using such an abrasive surface 32 to condition pad 10 is that portions of the pad itself may be worn away. Frequent contact between surface 32 and pad 10 may lead to a significant reduction in the amount of pad material available for polishing. As such, the life of the pad may be reduced, resulting in additional costs for replacing the pad.
Another pad conditioning technique relates to pressing a disk covered with diamond particles against the polishing pad while rotating both the pad and the disk. The diamond particle covered disk typically has a large diameter which may lead to problems during pad conditioning. For instance, the surface of the disk may be non-planar across its entire surface. Thus, due to variations across the polishing pad as a result of CMP, the disk may gouge portions of the polishing pad while insufficiently conditioning other portions of the pad. Yet further, diamond particles may separate away from the disk during CMP and become lodged in the pores of the polishing pad. Dislodged diamond particles could scratch the surface of semiconductor wafers while they are being polished. Since the features of integrated circuits are so minute, even the tiniest scratch may render devices of the integrated circuit inoperable or may destroy interconnections between various devices.
It would therefore be desirable to develop a CMP pad conditioning process which has less adverse effects on the CMP process. A conditioning process is needed which would result in less wear on the polishing pad, and would thus lead to the pad having a longer life. It is also desirable for pad conditioning to be performed uniformly across the entire pad surface. Uniform conditioning of the pad would promote uniform polishing of a semiconductor topography, and thereby enhance the CMP process. Moreover, a conditioning process in which pad abrasion is achieved without using particles that may break off and become embedded in the pad is necessary. As a result, damaging the surface of a semiconductor topography during CMP would be less of a possibility.